The present invention relates to a semiconductor device for use in high density-packaged modules, multichip modules, etc. and a wiring tape for use in preparation of the semiconductor device.
With recent trends to make electronic devices smaller in scale and higher in performance, a higher degree of integration, a higher density and a higher processing speed have been required for the semiconductor devices for use therein. Correspondingly, packaging procedures for the semiconductor devices have been also shifted from the pin insertion type towards the surface mount type. To meet higher pin counts, packages including DIP (dual inline package), QFP (quad flat package), PGA (pin grid array), etc. have been also developed.
However, QFP is provided with concentrated connection leads to a package substrate only at the peripheral region of the package and the leads per se are so fine that they are liable to deform, resulting in difficulty in packaging to meet the trend for higher pin counts. PGA has long and fine and highly dense terminals for connection to a package substrate, resulting in difficulty in realization of higher speed, and also is of a pin insertion type and thus incapable of attain surface packaging. That is, PGA has no advantage in case of high density packing.
To solve these problems and realize semiconductor devices capable of meeting higher speed requirements, a BGA (ball grid array) package having a stress buffer layer between the semiconductor chip and the wiring layer and also having ball-like connection terminals on the package substrate-facing side of the wiring layer has been recently developed (U.S. Pat. No. 5,148,265). In the package with this structure, the terminals for connection to the package substrate are of a ball-like solder, and thus there is no such lead deformation as in case of QFP, and distribution of terminals all over the package surface enables to make interterminal pitches larger and surface packaging easier. Furthermore, the connection terminals are shorter than those of PGA, and thus inductance components are smaller with accelerated signal speed, thereby enabling to meet the higher speed requirements.
For the stress buffer layer in the BGA package, an elastomer is used. Specifically, the stress buffer layer for a semiconductor device is provided in such a package structure comprising a wiring layer with a wiring formed on a support made from such an insulating material as polyimide, etc.; an elastomer of low elasticity such as silicone, etc., formed on the wiring layer; a semiconductor chip; and a substrate for heat radiation and for supporting a semiconductor device. Elastomer for the buffer layer can be formed by printing using a metal mask or by pasting a sheet-like elastomer. For formation of the buffer layer by printing, the following four steps are required: printing, heat curing, adhesive application and chip pasting. A heat set type, silicone elastomer material, when used, brings about such a problem as contamination of the wiring layer, packaging apparatuses, etc. due to evaporated components, etc. during the curing, thereby deteriorating the reliability in electrical connection between the semiconductor chip and the leads, when made therebetween. In pasting sheet-like elastomer, steam explosion due to steam absorbed during the package reflow occurs, thereby bringing about such problems as expansion of the package and peeling of the wiring layer.
An object of the present invention is to provide a semiconductor device having a high reliability and extremely less occurrence of failure at the package reflow in the above-mentioned semiconductor package structure.
According to a first aspect of the present invention, there is provided a semiconductor device, which comprises a semiconductor chip having a circuit-formed surface provided with a group of terminals thereon; a wiring layer comprising an insulating layer and a wiring for connecting the group of terminals to a group of external terminals provided on the surface of the insulating layer, the surface facing the circuit-formed surface of the semiconductor chip; a three-layered buffer layer provided between the circuit-formed surface of the semiconductor chip and the wiring layer, the buffer layer comprising a structure having interconnected foams, an adhesive layer provided on the semiconductor chip-facing side of the structure having interconnected foams, directed to pounding to the semiconductor chip and another adhesive layer provided on the other side of the structure, directed to bonding to the wiring layer; a sealant for sealing connections of the group of terminals provided on the semiconductor chip to the wiring layer; and the group of external terminals connected to the wiring layer.
According to a second aspect of the present invention, there is provided a wiring tape for a semiconductor device, which comprises a wiring layer comprising an insulating layer and a wiring on an insulating layer, one end of the wiring being connected to terminals on the semiconductor chip and the other end of the wiring being connected to external terminals for connecting to a package substrate; and a three-layered buffer layer bonded to the wiring-provided side of the wiring layer, the buffer layer comprising a structure having interconnected foams, an adhesive layer provided on the semiconductor chip-facing side of the structure having interconnected foams, directed to ponding to the semiconductor chip and another adhesive layer provided on the other side of the structure, directed to bonding to the wiring layer.